In accordance with the present invention, an FPGA input/output buffer
including a tristate enable register is provided. A bus line provides the
FPGA output through a tristate buffer to the pad or pin. A register
controls the state of the tristate buffer. A register for providing an
input signal from the pad or pin may also be provided. By placing an
address on address lines controlling the register clocks, any selected one
of the input/output buffers can be accessed. In one embodiment, separate
addresses are provided for loading a tristate control value into the
output control register and for loading data into the input register.