To improve the processing speed in a case where a program requiring memory access
serialization is executed in a multiprocessor environment with a load instruction
out-of-order execution function.
Each of CPUs has the function of performing store forwarding (SF) when the address
regions of a pair of store and load instructions coincide with each other. Each
CPU stops SF and performs store forwarding avoidance (SFA) when the two address
regions do not coincide with each other but have an overlap therebetween. Each
of SF and SFA is executed with priority over out-of-order execution. Each CPU performs
SFA effective in limiting out-of-order execution with respect to a predetermined
store instruction on a program and a load instruction mated to the store instruction
and given after the store instruction, and ensures that data relating to the store
instruction can be observed from other CPUs.