A microprocessor apparatus is provided that enables write back and invalidation
of a block of cache lines from memory. The apparatus includes translation logic
and execution logic. The translation logic translates a block write back and invalidate
instruction into a micro instruction sequence that directs a microprocessor to
write back and invalidate a block of cache lines from cache to memory, where the
number of cache lines in the block has been previously entered in a register in
the microprocessor by a preceding micro instruction. The execution logic is coupled
to the translation logic. The execution logic receives the micro instruction sequence,
and issues transactions over a memory bus that writes back data corresponding to
each of the cache lines within the block.