A synchronous flash memory includes an array of non-volatile memory cells. The
memory device has a package configuration that is compatible with an SDRAM. The
memory device in one embodiment can comprise control circuitry to perform an initialization
operation on the synchronous memory, and a status register having at least one
data bit that can be programmed to indicate if the initialization is being performed.
A method of operating a memory system includes initiating an initialization operation
on a memory device, and monitoring a memory status register to determine when the
initialization operation is completed.