A memory control circuit includes a control register having a memory capacity
of
m bits or smaller for setting information necessary for controlling the memory,
input pins to which m-bit test data is input in parallel, an extension circuit
for extending the data input to the input pins to n-bit data, and a first selection
section for selectively inputting n-bit data supplied from the extension circuit
or a CPU based on a mode signal to switch between a test mode and a normal mode.
The memory control circuit further includes a degeneration circuit for compressing
n-bit data to be output in parallel to the CPU to m-bit data, a second selection
section for selecting m-bit data compressed by the degeneration circuit or lower
m-bit data in n-bit data to be output to the CPU based on a switch signal, and
output pins for outputting the m-bit data selected by the second selection section
in parallel.