A semiconductor memory device having a mode register set (MRS) includes: a
decoding unit for decoding a plurality of address signals included in the
MRS and outputting a plurality of decoded signals; and an output unit for
outputting a plurality of configuration signals and activating one of the
plurality of configuration signals in response to the plurality of
decoded signals, wherein the output unit keeps its previous output
signals if more than one of the plurality of decoded signals are
activated.