A method of implementing a user integrated circuit (IC) design in a tree
representation includes the step of introducing the tree representation
for the user IC design in a partitioned manner including at least one
sub-design to form a design abstraction of the user design. At least one
sub-design can include a sub-design providing for multiple levels of
implementation hierarchy. The method can further include the step of
traversing the design abstraction in a top-down fashion to provide
functions selected among floor planning, port assignment, and timing
budgeting for at least one sub-design, and the step of traversing the
design abstraction in a bottom-up fashion to facilitate at least one
among resolution of resource conflicts and parallel processing of
multiple sub-designs. Traversing the design abstraction in the bottom-up
fashion can facilitate a re-budgeting of timing for the integrated
circuit design.