A method of forming a metal line in a semiconductor device. The method
includes forming an insulating interlayer over a substrate provided with
a lower metal line, and forming a hole exposing the lower metal line. The
method also includes forming a first metal layer on the insulating
interlayer including an inside of the hole and the lower metal line,
forming a conductor layer on the first metal layer to fill the hole, and
etching back the conductor layer to form a plug until the first metal
layer is exposed. The method further includes stacking a second metal
layer and a third metal layer on the first metal layer, and patterning
the second metal layer, the third metal layer, and the first metal layer
to form an upper metal line overlapped with the plug using an etch mask
defining the upper metal line.