A processing circuit for a sync signal includes a trial circuit and a
windowing circuit. The trial circuit includes a counter that generates a
count value proportional to the duration between successive sync pulses.
When the count value reaches a trial sync spacing count value, a trial
window signal is created and the counter is reset. If a predetermined
number of subsequent sync pulses occur within the trial window signal,
the sync spacing count value is confirmed and stored in a sync spacing
register. The windowing circuit includes a counter that generates a count
value proportional to the duration between successive window signals, and
compares the count value to the value stored in the sync spacing register
to generate a window signal. The window signal is compared with the sync
signal pass valid sync signals.