A memory interleave system includes M (M=2.sup.p, where p is a natural
number) memory banks, M memory control units (MCU) corresponding
respectively to the M memory banks, N (a natural number) CPUs, and N
address generating units (AGU) corresponding respectively to the N CPUs.
Each memory bank includes a plurality of memories. The CPUs output memory
requests, each containing a first bank address (address of the memory
bank) and a first intra-bank address (address of a memory in the memory
bank). Each AGU receives a memory request from a corresponding CPU, and
generates and outputs a second intra-bank address and a second bank
address by using the first intra bank address and the first bank address.
Each memory control MCU performs memory bank access control on the basis
of the second intra-bank address. An MCU performing access control is
selected on the basis of the second bank address.