Methods and apparatus provide for controlling an SRAM memory, the SRAM
memory including a plurality of memory cells arranged in an array of rows
(word lines) and columns (bit lines), including: mirroring logic values
of at least one of the bit lines to a global bit line; driving the global
bit line to a pre-charge logic value in response to a clock signal that
cycles at least one time during successive read and write operations to
the memory cell; maintaining the global bit line at the pre-charge logic
value during a write operation in which a logic value is written to the
bit line that is opposite to the pre-charge logic value.