A test head performs at-speed testing of high serial pin count gigabit per
second (GBPS) devices. The test head includes a device under test (DUT)
coupled to a first portion of the test head and a rider board coupled to
the DUT. The rider board includes a first signal path including switching
matrices coupled to the DUT, a second signal path including bit error
rate testing (BERT) engines, each of the BERT engines being coupled to
each other, corresponding ones of the switching matrices, and to the DUT,
and a third signal path including Ethernet testing circuits coupled to
the DUT. The BERT engines allow for routing of a test signal from any of
the switching matrices to any other switching matrix (e.g., between
non-adjacent switching matrices).