A memory cell comprises a wordline, a first digital inverter with a first
input and a first output, and a second digital inverter with a second
input and a second output. Moreover, the memory cell further comprises a
first feedback connection connecting the first output to the second
input, and a second feedback connection connecting the second output to
the first input. The first feedback connection comprises a first
resistive element and the second feedback connection comprises a second
resistive element. What is more, each digital inverter has an associated
capacitance. The memory cell is configured such that reading the memory
cell includes applying a read voltage pulse to the wordline. In addition,
the first and second resistive elements are configured such that the
first and second feedback connections have resistance-capacitance induced
delays longer than the applied read voltage pulse.