Part of the latency from memory read or write operations is for data to be
input to or output from the data latches of the memory via an I/O bus.
Methods and circuitry are present for improving performance in
non-volatile memory devices by allowing the memory to perform some of
these data caching and transfer operations in the background while the
memory core is busy with an erase operation. In the exemplary embodiment,
a read operation is inserted just prior to the erase operation or one or
more read operations are inserted during a soft programming phase of the
erase operation. In this way, the read data could be output while the
erase operation is taking place, thereby making use of otherwise waiting
time.