A method for designing a multi-threaded processing operation that
includes, e.g., multimedia encoding/decoding, uses an architecture having
multiple processors and optional hardware accelerators. The method
includes the steps of: identifying a desired chronological sequence of
processing stages for processing input data including identifying
interdependencies of said processing stages; allotting each said
processing sage to a processor; staggering the processing to accommodate
the interdependencies; selecting a processing operation based on said
allotting to arrive at a subset of possible pipelines that offer low
average processing time; and, choosing one design pipeline from said
subset to result in overall timing reduction to complete said processing
operation. The invention provides a multi-threaded processing pipeline
that is applicable in a System-on-Chip (SoC) using a DSP and shared
resources such as DMA controller and on-chip memory, for increasing the
throughput. The invention also provides an article which is programmed to
execute the method.