A Wide Register Set (WRS) is used in a packet processor to increase
performance for certain packet processing operations. The registers in
the WRS have wider bit lengths than the main registers used for primary
packet processing operations. A wide logic unit is configured to conduct
logic operations on the wide register set and in one implementation
includes hardware primitives specifically configured for packet
scheduling operations. A special interlocking mechanism is additionally
used to coordinate accesses among multiple processors or threads to the
same wide register address locations.The WRS produces a scheduling engine
that is much cheaper than previous hardware solutions with higher
performance than previous software solutions. The WRS provides a small,
compact, flexible, and scalable scheduling sub-system and can tolerate
long memory latencies by using cheaper memory while sharing memory with
other uses. The result is a new packet processing architecture that has a
wide range of cost/performance points, based on desired scheduling
requirements.