If a clock signal ck is "H" and an input pulse signal in (first control
signal) is "H", then n-type transistors M15 and M16 are turned on to make
an output node/OUT have the GND level. Then, a p-type transistor M12 is
turned on to make an output node OUT have a Vcc (16 V) level. Thus, a
latch circuit LAT operates as a level shifter circuit when first and
second control signals and the clock signal ck are at "H" and operates as
a level hold circuit in any other case. Therefore, the shift register
circuit constructed of the latch circuit LAT functions as a low-voltage
interface, and the input of the clock signal ck is stopped when the latch
circuit LAT is inactive, so that the load and the consumption of power of
the clock signal line are reduced.