A semiconductor device determines whether a clocking signal intended for latching an event at the designated location is absent, and if so, information about the event that occurred in the absence of the clocking signal may be provided at the another location. The semiconductor device, in one embodiment, includes first and second clock domains capable of receiving first and second clocks, respectively. When deployed in a processor-based system, one or more interrupting events may be registered. The semiconductor device further comprises an interface to capture the interrupting events based on a control logic implementing a mechanism (e.g., a state machine) capable of remembering information associated with the interrupting events that may occur when the first clock may be temporarily absent. When the first clock restarts, a register subsequently records the information associated with the interrupting events that may have occurred.