A multithreaded processor includes an interrupt controller for processing a cross-thread
interrupt directed from a requesting thread to a destination thread. The interrupt
controller in an illustrative embodiment receives a request for delivery of the
cross-thread interrupt to the destination thread, determines whether the destination
thread of the cross-thread interrupt is enabled for receipt of cross-thread interrupts,
and utilizes a thread identifier to control delivery of the cross-thread interrupt
to the destination thread if the destination thread is enabled for receipt of cross-thread
interrupts. The requesting thread requests delivery of the cross-thread interrupt
to the destination thread by setting a corresponding interrupt pending bit in a
flag register of the multithreaded processor. The destination thread is enabled
for receipt of cross-thread interrupts if a corresponding enable bit is set in
an enable register of the multithreaded processor. The flag and enable registers
may be implemented within the interrupt controller.