A computer implemented process of inserting enhanced scan bypass in relation to a bypassed block in an integrated circuit design comprising: receiving an HDL description of the circuit design; wherein the HDL description includes a port specification HDL instruction that specifies port properties of a bypassed block; wherein the HDL description includes an enhanced bypass HDL instruction that specifies how many scan cells to provide per port of the bypassed block in a scan bypass circuit that bypasses the bypassed block; wherein the bypass HDL instruction includes a user-selectable option of at least zero or one or two scan cells per port; in response to the specification HDL instruction and the enhanced bypass HDL instruction, automatically generating a netlist portion that includes scan a bypass circuit that bypasses the bypassed block and that includes the specified number of scan cells per port.

 
Web www.patentalert.com

< System of and method for decoding trellis codes

< Systems and methods for digital document processing

> Changeable machine readable assaying indicia

> Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's

~ 00225