The load limit on each path to avoid EM is estimated and provided as an
input to various early design stages (such as placement and routing).
Each (of one or more) of the early stages may ensure that the load limit
is not violated. Techniques such as increasing the path width and
inserting additional circuit (e.g., a buffer cell) in the path, may be
employed to avoid the EM violations. As a result, unneeded iterations of
design stages may be avoided for purposes of EM checks alone.