In one embodiment, a processor is configured to execute a window swap
instruction. The processor comprises a register file (that comprises a
plurality of registers) and first and second execution units coupled to
the register file. A first pipeline associated with the first execution
unit has a first number of pipeline stages, and a second pipeline
associated with the second execution unit has a second number of pipeline
stages. The first execution unit is configured to change the current
register window from the first register window to the second register
window in the register file in response to the instruction. The second
execution unit is configured to perform an operation defined by the
instruction and write the result to the register file. The second number
of pipeline stages exceeds the first number, whereby the second register
window is established in the register file prior to writing the result.