Data not stored in the DRAM array of a SDRAM module is read from the SDRAM
module in a synchronous data transfer. The data transfer, referred to as
register read command/operation, resembles a read command/operation
directed to data stored in the DRAM array in timing and operation. The
register read command is distinguished by a unique encoding of the SDRAM
control signals and bank address bits. In one embodiment, the register
read command comprises the same control signal states as a MSR or EMSR
command, with the bank address set to a unique value, such as 2'b10. The
register read command may read only a single datum, or may utilize the
address bus to address a plurality of data not stored in the DRAM array.
The register read operation may be a burst read, and the burst length may
be defined in a variety of ways.