A shift register includes a plurality of stages each of which has a first pull-up driving part to generate a first control signal in response to an output signal of an adjacent previous stage or a control signal, a pull-up part to generate a current output signal in response to a first clock signal and the first control signal, a second pull-up driving part to generate at least one second control signal in response to the first clock signal and a second clock signal, a third pull-up driving part connected to a low level terminal to operate in response to an output signal of an adjacent following stage, and a pull-down part to operate in response to the second clock signal.