A circuit design program product to cause a computer to execute a circuit design process based on a test point insertion, includes: a step for making reference to a netlist to extract a plurality of equivalent faults f.sub.j; a step for searching a number n(f.sub.j) of test point required for a number of the equivalent fault keeping equivalent relation with a search object equivalent fault f.sub.j with each of a plurality of equivalent faults as the search object equivalent fault to become a predetermined number and a insertion position G(f.sub.j); a step for calculating probability p(f.sub.j) of a single stuck-at fault being included in a set of equivalent faults including at least a search object equivalent fault f.sub.j at an occasion when the relevant stuck-at fault takes place in the circuit; a step for calculating a parameter e(f.sub.j) derived by an equation: e(f.sub.j)=p(f.sub.j)/n(f.sub.j) on each pattern of an insertion position G(f.sub.j); and a step for determining the insertion position G(f.sub.max) giving the maximum value among the calculated parameters e(f.sub.j) as a position where the test point is inserted.