A circuit and method for reducing error in a delay locked loop (DLL) in which a plurality of outputs, each establishing a boundary between two consecutive phases, is accomplished by averaging an error present in one of the outputs over at least two phases established by the outputs. A pair of inverters are used to drive fight during a definable time period, which enables the circuitry to average the error over at least two phases, thus distributing the error that was present in one phase over at least two phases.