A method and apparatus determines interleaving schemes in a computer system that supports multiple interleaving schemes. In one embodiment, a memory interleaving scheme lookup table is used to assign memory interleaving schemes based on the number of available bank bits. In another embodiment, the percentage of concurrent memory operations is increased by assigning memory interleaving schemes to bank bits based on the classification of bank bits. The present invention supports a memory organization that provides separate memory busses that support independent simultaneous memory transactions, and memory bus segments that allow memory read operations to be overlapped with memory write operations, with each memory bus segment capable of carrying single memory operation at any given time. Bank bits that distinguish between memory busses are classified as class A, bank bits that distinguish between memory bus segments are classified as class B, and bank bits that distinguish between banks on a single memory bus segment are classified as class C. The memory controller supports multi-cache line interleaving (MCI), cache effect interleaving (CEI), and DRAM page interleaving (DPI). The memory operations associated with MCI tend to be independent, simultaneous, and unrelated. Therefore, class A bank bits are optimally allocated to MCI. The memory operations associated with CEI tend to occur in read/write pairs. Therefore, class B bank bits are optimally allocated to CEI. The memory operations associated with DPI tend to be serial in nature, and tend to be of the same type. Therefore, class C bank bits are optimally allocated DPI. In one embodiment, banks bits are assigned to memory interleaving schemes based on the classification of the bank bits using a memory interleaving scheme lookup table. In another embodiment, an algorithm is used to assign bank bits to interleaving schemes.