A method for debugging an application on an embedded processor using a debug monitor service routine (debug ISR) and allowing critical interrupts to be transparently serviced is provided. The method enters and runs a debug monitor service routine transparently such that the application program being debugged is unaware of the monitor. A debug interrupt is completely transparent to the application software that runs on the embedded processor and is therefore non-maskable. In addition, when entering the debug ISR, shadow registers and the global interrupt disable bit (if they exist) are not be altered, which preserves the monitor's transparency to the application. Once the debug monitor is entered, a context save may be performed if needed and the monitor may proceed to enable interrupts if necessary. Using a second global interrupt enable/disable mechanism, distinct from, and in series with, the normal global interrupt enable/disable mechanism, the debug ISR can decide to enable or disable global interrupts. If an interrupt does occur while the debug monitor is running and interrupts are still enabled, that interrupt is serviced transparently to the debug monitor. Once the debugger releases the monitor it may exit, in a single atomic operation which avoids confusing a regular return from interrupt with a debug return from interrupt. If the debug monitor does not need to do a context save upon entering the debug ISR, the processor may be set to operate in mode where interrupts are not disabled upon entry into the debug ISR. However, the monitor may always opt to disable interrupts once the debug ISR is running. Upon exiting the debug ISR, the second global interrupt enable/disable mechanism is set to enable interrupts, thereby preserving the status of the normal global interrupt enable/disable mechanism.