A microprocessor (5) including a plurality of write buffers (30) of varying sizes is disclosed. The varying sizes of the write buffers (30) allow for each write transaction from the core of the microprocessor (5) to be assigned to the most efficient write buffer size. Each write buffer (30) also includes sequential control logic (50) that issues a status code indicating the extent to which its write buffer (30) is filled; the control logic (50) advances to a more full state responsive to receiving a new data transaction from the internal bus, and advances to a more empty state responsive to completing a write transaction to the external bus. Each write buffer (30) communicates data from an internal bus (PBUS) to an external bus (BBUS) in a manner that is synchronized in the control path, rather than in the data path. Clock domain translation circuitry (65) is included within timing control circuitry (62) to translate the control signal from one clock domain to another, thus ensuring that overlapping writes do not occur. Internal snoop control circuitry (71) is also provided, for controlling access to the write buffers (30) so that memory reads missing in on-chip cache may be performed to the write buffers (30), rather than to main memory (21), if the data remains resident therein. A read buffer (33) is also disclosed, and has a plurality of entries for receiving blocks of data from the external bus (BBUS); upon receipt of a block of data, the read buffer (33) indicates the presence of data therein to the core of the microprocessor (5) to initiate its retrieval for execution of an instruction.