A test circuit that includes a scan path having serially coupled scan flip-flops clocked by a system clock signal, an index counter clocked by the system clock for providing an index output for tracking data in the scan path, a control circuit clocked by a test clock signal for receiving scan input data from an external source and for providing output data to the external source, an input memory for receiving scan input data from the control circuit, an output memory for receiving the output of the scan path, and a selection circuit having a first input for receiving the output of the scan path, a second input for receiving scan input data from the input memory, and an output connected to the input of the scan path.

_ uno prueba circuito que incluir uno explorar trayectoria tener serial coupled explorar flip-flop registrar por uno sistema reloj señal, uno índice contador registrar por sistema reloj para providing uno índice salida para tracking dato en explorar trayectoria, uno control circuito registrar por uno prueba reloj señal para receiving explorar entrada dato uno externo fuente y para providing salida dato externo fuente, uno entrada memoria para receiving explorar entrada dato control circuito, uno salida memoria para receiving salida explorar trayectoria, y uno selección circuito tener uno primero entrada para receiving salida explorar trayectoria, uno segundo entrada para receiving explorar entrada dato _ entrada memoria, y uno salida conectar entrada explorar trayectoria. _