A method of maintaining cache coherency when a value is shared in one or more caches and an invalidation request for the corresponding memory block is issued, by sending a combined response to a requesting device indicating that it may proceed with a requested transaction, and reissuing the invalidation request in a background manner to any cache which responded with a shared/busy response. The invalidation request may be placed in a background kill queue, and later bus transactions compared with entries of the background kill queue to maintain the integrity of the target memory block. The requesting device's processor may continue to perform subsequent loads and stores to the line while other devices must wait for the background kill to complete before receiving control of the line.