In a semiconductor integrated circuit device, a pattern generator 12 generates burn-in test patterns based on control signals received through external terminals 11 and corresponding I/O buffers, and provides the generated burn-in test patterns to input terminals 5 of a DRAM 2. The burn-in test operation is performed only by using the control signals received through the external terminals 11 and the corresponding I/O buffers. The burn-in test operation is performed by a small number of access operations to the I/O buffers because the number of the access operations to the I/O buffers may be decreased when comparing with a conventional one. Thereby, the accuracy of the reliability test for the DRAM 2 may be increased.