A method and apparatus for having a reduced number of controlling system microprocessors in a device. In one embodiment, the present invention includes a single main system microprocessor. This embodiment further includes an impedance isolating expansion circuit. The single main system microprocessor and the impedance isolating expansion circuit are coupled together using a bus. In this embodiment, the bus has a plurality of components coupled thereto. Additionally, in the present embodiment, a plurality of second components are coupled to the impedance isolating expansion circuit such that the plurality of second components are not directly connected to the bus and such that the plurality of second components do not induce a direct impedance load on the bus. By prohibiting the second components from inducing a direct impedance load on the bus, the present invention allows the single main system microprocessor to operate effectively and without severe signal distortion. As a result, a single main system microprocessor is able to control operation of a device with reliability and stability even when the device includes numerous components.