An integrated memory in which the plate lines run parallel to the bit lines and are driven by the column decoder. The effect achieved by the fact that each plate line is connected to the memory cells of the associated bit line is that only those memory cells whose associated bit line is required for the respective memory access are affected by the pulsed signals of the plate line. Therefore, only the potential of that bit line which is currently required for a data transfer is influenced by pulsed signals on the associated plate lines.