A bus capture circuit captures digital signals applied on respective lines
of a bus. The bus capture circuit includes a clock delay circuit that
generates an internal clock signal responsive to an external clock signal.
The internal clock signal has a fixed delay relative to the external clock
signal and is applied to clock a plurality of latches. Each latch latches
a digital signal applied at the input terminal responsive to the internal
clock signal from the clock delay circuit. The bus capture circuit further
includes a plurality of signal delay circuits, each being coupled between
a respective bus line and the input terminal of a respective latch. Each
signal delay circuit develops a delayed digital signal having a delay time
relative to the digital signal applied on the corresponding bus line, and
applies the delayed digital signal to the input terminal of the
corresponding latch. A control circuit adjusts the delay time of each
signal delay circuit as a function of the data eye of the digital signal
applied on the input of the signal delay circuit. The corresponding latch
successfully latches the delayed digital signal output from the
corresponding signal delay circuit. The bus capture circuit may also
operate in a monitoring mode during normal operation of a packetized
memory device to detect shifts in the data eye of an external command
clock signal applied to the packetized memory device and adjust the delay
time of all signal delay circuits when such a shift is detected.