A designer's timing diagram editor tool set provides programs for logic verification at logic design level. External stimulus to the design is done by a set of irritator programs created by the designer and derived from timing diagrams describing the input signals to be driven and/or the output signals to be checked of the logic under test. A timing diagram editor provides a graphical user interface that allows the logic designer to describe his or her logic in a general timing diagram format. Timing diagrams are then compiled into stand-alone executable programs. Sets of one or more executable timing diagrams (called buckets) can be defined. A simulation driver reads in the bucket file specified and randomly selects timing diagrams to stimulate the design under test with legal scenarios described in the timing diagrams.