Provided is a printed wiring board for a chip size scale package, which overcomes the poor adhesion of solder balls to a base material which poor adhesion is caused by a recent decrease in the size of the solder balls, and in the chip size scale package, the distortion of the printed wiring board is decreased and the distortion of a semiconductor package formed by mounting a semiconductor chip on the printed wiring board by wire bonding or flip chip bonding is decreased. The printed wiring board has, as a substrate for a chip scale package, a double-side copper-clad laminate formed of an insulation layer and having copper foils on both surfaces, wherein the double-side copper-clad laminate has an upper copper foil surface and a lower copper foil surface, the upper copper foil surface has a wire bonding or flip chip bonding terminal and has a copper pad in a position where the copper pad can be electrically connected to said wire bonding or flip chip bonding terminal and can be connected to a blind via hole formed in the lower copper surface, the lower copper foil surface has a solder-balls fixing pad in a position corresponding to said copper pad, the solder-balls-fixing pad has at least 2 blind via holes within itself, and the solder-balls-fixing pad connected to a reverse surface of the copper pad with a conductive material is electrically connected with solder balls which are melted and filled in blind via holes so as to be mounded.