The invention is a method and apparatus that verifies the design of electronic circuitry containing a function to be tested. An input, such as a random input, is provided to the electronic circuitry containing the function, yielding an output. This output, in turn, is used as input (denominated "inverse input") to an inverse of the function to be tested. The resulting output (termed "inverse output") is compared to the original input to the function to be tested to facilitate verification of the design of the circuitry.