An electrical rules checker system and method are provided to report any errors discovered during appraisal of an element at a node in a netlist. In accordance with one aspect of the invention, a method selects a circuit configuration to be identified. Next, identify any element at a node, equal to or virtually equal to said circuit configuration. Then, the element equal to and virtually equal to said circuit configuration is appraised. Finally, any error discovered during appraisal of the element at the node is reported. hi accordance with another aspect of the invention, a system is provided for appraising tri-state logic connected to a selected node of an integrated circuit. The system operates by a code segment selecting a circuit configuration to be identified. A second code segment identifies any element at a node, equal to said circuit configuration, and a third code segment identifies any element at the node virtually equal to said circuit configuration. A fourth code segment appraises the element equal to and virtually equal to the circuit configuration, and a fifth code segment reports any error discovered during appraisal of the element at the node.