An RTL description, such as a Verilog description, of an integrated circuit is derived from a C/C++ description by defining the integrated circuit as a generalized multiplexer having outputs and two groups of input variables X.sub.1, X.sub.2, . . . , X.sub.s and Y.sub.1, Y.sub.2, . . . , Y.sub.n in which each variable X.sub.1, X.sub.2, . . . , X.sub.s, is fixed and no output depends on more than one variable of Y.sub.1, Y.sub.2, . . . , Y.sub.n. An output vector is constructed by Exclusive-OR operations to find an index j for UU1=(BIT(0,j), BIT(1,j), . . . , BIT(K-1),j)). The Verilog description of the circuit is a function of the solution of the output vector, or a constant.