A memory unit 18 includes a bus 16 which couples the memory unit to a memory control unit 14. The memory unit includes a latch for receiving and storing an address from the bus, a first memory plane for storing information units associated with an odd address, a second memory plane for storing information units associated with an even address, an input latch for receiving from the bus an information unit associated with a received address and output latches for storing, prior to transmission to the bus, a stored information unit associated with a received address. The memory unit further includes logic, responsive to a state of a first bus signal line, for enabling the output latches to (a) simultaneously transmit to the bus an information unit from both the first and the second memory planes, or (b) sequentially transmit to the bus an information unit from one of the memory planes followed by an information unit from the other one of the memory planes.