Several peripheral entities are provided, with each peripheral entity being
clocked by its own internal clock signal and being able to access a
single-access memory. A priority entity is defined from among the
peripheral entities, and the other peripheral entities are defined as
auxiliary entities. A repetitive time frame is formulated, regulated by
the internal clock signal of the priority entity, and subdivided into
several groups of time windows that are allocated to the peripheral
entities. One of the peripheral entities is a microprocessor that is
disabled for a fixed duration after each memory access request.