A method and apparatus for developing run-time parameterizable logic cores for programmable logic devices (PLDs). In various embodiments, logic cores are defined in a run-time reconfiguration program, the logic cores having output pins and input pins. A pre-route tool routes selected ones of the output pins to selected ones of the input pins and generates program code for the run-time reconfiguration program. The program code generated by the pre-route tool programs interconnect resources that make the required connections. The automatically generated program code is then parameterized and included in the run-time reconfiguration program.