A circuit synthesis method includes the steps of converting a behavioral description describing a behavior of calculation processing into a control data flowgraph; assigning a plurality of calculations, at least one input and at least one output in the control data flowgraph into a plurality of prescribed time slots; assigning the plurality of calculations, a plurality of data dependency edges, the at least one input and the at least one output respectively to a plurality of calculation devices, at least one register, at least one input pin and at least one output pin; generating a plurality of paths corresponding to the plurality of data dependency edges; detecting a feedback loop formed of at least two of the plurality of paths and at least one of the plurality of calculation devices; and re-assigning one calculation, which has been assigned to a first calculation device included in the feedback loop, to a second calculation device among the plurality of calculation devices, so as to delete the feedback loop.