A signal processor with an instruction set architecture (ISA) for flexible data typing, permutation, and type matching of operands. The signal processor includes a data typer and aligner to support flexible data typing, permutation and type matching of operands of the instruction set architecture. The data typer and aligner is selectively configued to align and select one of more sets of data bits from one or more data buses as operands for functional blocks of the signal processor in response to fields of an instruction.