A cell generator for UTMC's gate array library of core logic cells is implemented using Cadence.RTM. Relative Object Design (ROD) software. The ROD functions use design rules to create and align ROD objects. Design rules can be specified for different foundries and technologies, or can be altered to special design requirements. ROD user-defined handles are created to facilitate internal routing and to accommodate different UTMC architectures. Hierarchy is used to minimize the ROD code, and a Cadence.RTM. SKILL Makefile generates the entire library automatically.