A system, device, and method for dynamically testing integrated circuits is disclosed. The system includes a first integrated circuit including input pins, output pins, normal operating logic, and control logic. The control logic is connectable to the input pins and configured to initiate a test interval based on a state of the input pins and to record the state of the input pins during the test interval. A second integrated circuit of the system includes input pins, output pins, normal operating logic, and test control logic. The control logic connectable to the output pins and configured to generate a user programmable set of test output signals. At least some of the output pins of the second integrated circuit are connected to at least some of the input pins of the first integrated circuit. The test control logic of the first integrated may be configured to initiate the test interval when the state of the input pins matches a predefined state. A portion of the test control logic of the first and second devices may be driven by a system clock that drives the operating logic such that the test output signals of the second device and the test input signals of the first device transition at the frequency of the system clock during the test interval. The test output signals may transition among one of a set of possible test output states, wherein the possible test output states include a predetermined pattern, an inverse of the predetermined pattern, an all 0's pattern, and an all 1's pattern.