A memory system having a common memory region, such memory region including pair of control ports and a common DATA port. A switching network is provided having a pair of information ports, for: coupling information having a control portion and a DATA portion between: a first one of such pair of information ports; and, a first one of the control ports and the DATA port through a first switch section; and coupling information having a control portion and a DATA portion between: a second one information ports; and, a second one of the control ports and the DATA port though a second switch section. A pair of clocks is included. A first one of such clocks is fed to operate the first switch section in coupling the information through such first section and a second one of such clocks being fed to operate the second switch section in coupling the information through such first section. The memory system includes: (A) a memory array region for storing information, such memory array region having: (a) a DATA port; (b) a pair of memory control ports; (B) a pair of logic sections, each one thereof having: (a) a logic section control port connected to a corresponding one of the pair of memory control ports for providing memory control signals to the memory array region, and, (b) a logic section DATA port, and (c) wherein the logic section DATA ports of the pair of logic sections are connected together and to the memory array DATA port; and, (C) a pair of independent clocks, each one of such clocks being coupled to a corresponding one of the logic sections to provide clock signals to such one of the logic sections.