According to one embodiment, a method of conducting a switching state (AC) loop back test at a buffer circuit comprises varying the relationship between the generation of strobe signals at a strobe input/output (I/O) circuit of a first group of I/O circuits and the reception of data at the first group of I/O circuits receiving the strobe signals fails, and comparing the time at which the first I/O circuit fails with a predetermined timing performance for the first group of I/O circuits. Subsequently, it is determined whether the first group of I/O circuits satisfies the predetermined timing performance.

 
Web www.patentalert.com

< (none)

< Apparatus and method for configuring a programmable logic device with a configuration controller operating as an interface to a configuration memory

> Mechanism for optimizing processing of client requests

> (none)

~ 00084