Delay and/or load estimation is performed prior to physical layout in an
integrated circuit (IC) design process. Initially, a description of the IC
design is obtained, the description being in a hardware description
language (HDL). Floor planning is then performed based on the HDL
description, and buffers are inserted into the IC design based on such
floor planning. Finally, delays and/or loads are estimated in the IC
design while taking into account the effect of the buffers. The buffers
are inserted in the foregoing processing based on anticipated processing
later in the IC design process.